The control of multiple, accurately-spaced clock phases operating at one frequency is important to the design of many high-performance, high-speed chip-to-chip interconnect systems. While some interconnect systems use just two phases, e.g., the rising and falling edges of a single very high-speed clock, there are drawbacks to that approach, such as the difficulty of accurately controlling the duty-cycle of such a high-speed clock, as well as the necessity and difficulty of operating the high speed clock at a high frequency equal to ½ the data rate. The use of multiple clock signals with accurately spaced clock phases overcomes the disadvantages of a single clock approach. For example, because there are more clock phases, the frequency of these multi-phase clocks can be a fraction of the data rate, such as ½, ¼, ⅛, or 1/10. However, with multiple clock signals, problems can develop if the phase relationship among the various clock signals is not properly and accurately maintained.